About the Company: 
Founded in 2013, headquartered in Santa Clara, and backed by Andreessen Horowitz, Lightspeed Venture Partners, and Sequoia Capital, the company designs and produces programmable network switch silicon, systems, and software. The team comprises visionaries, experienced technologists, and engineers who have created a blueprint for designing and operating the world’s fastest and most programmable networks.

What You’ll Be Doing:

• Identifying blocks suitable for Formal

• Working with block designers to understand micro-architectural details

• Identifying and implementing Formal properties

• Applying abstraction techniques

• Signing off with bound analysis and coverage

• Participating in test-plan and test-bench reviews

To be successful in this role, you'll need the following:

• Bachelor's degree or higher in Electrical or Computer Engineering, Computer Science, or related field.

• 6+ years of experience with RTL designs (either in design or verification)

• Experience with System Verilog, System Verilog Assertion Language (SVA), or equivalent

• Understanding of Formal verification concepts

• Experience with the application of Formal Verification techniques, including abstractions

• Hands-on experience with industry-standard Formal verification tools

• Familiarity with bug-hunting strategies and coverage analysis

• Experience with various FV tool apps (C vs. RTL, RTL-to-RTL equivalence, Connectivity)

• Profound understanding of Formal Verification engines

• Proficiency in scripting languages. e.g., Python/Perl/TCL

What is Being Offered:

• Best-in-class compensation

• Annual + Quarterly bonuses, stock programs

• Cutting-edge health plan options

• Generous time off

• Life-long career growth opportunities

• Education benefits: tuition assistance, classroom and online learning resources, career advisers

• Relocation assistance

• Flexible work options, job rotation programs

• Wellness programs + Employee Assistance Plans/Programs