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IP Design Verification Manager

Job description

About the Company: 
American multinational corporation and technology company headquartered in Santa Clara, California, is the world's largest semiconductor chip manufacturer by revenue. The team's unmatched depth of experience and scope of vision allows it to dream big, to create the future of computing and communications—including powerful processors and accelerators that unlock the full potential of data. Continuously delivering advances in performance, power, and connectivity across a diversity of data-centric workloads, so its customers can harness the raw power of data. Company innovations span architecture, memory, software, and security to help develop transformative products and experiences for its customers. 107,000 employees worldwide are working together to enable unique experiences in 5G, artificial intelligence, driverless cars, and much more.

What You’ll Be Doing:

  • You will lead a talented technical team chartered to build efficient and effective constrained-random verification environments that thoroughly exercise complex IP blocks. 

  • Your team will be responsible for the full life cycle of verification, from planning to test execution, including collecting and closing coverage. 

  • You and your team will conduct/participate in test plan and test reviews, develop verification components and tests, and triage failures. In addition to managing complex verification project schedules, dependencies, and deliverables, you will be expected to mentor, provide technical guidance, and develop the team.

  • Experience providing effective, hands-on, technical leadership in a results-oriented team environment

  • Excellent written communication skills

  • Good collaboration skills to interface with architecture, design, and system validation stakeholders.

To be successful in this role, you'll need the following:

  • Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field and 6+ years of industry work experience (Master’s Degree or higher preferred)

  • 6+ years of experience in architecting and developing testbenches and verification components like bus functional models and scoreboards/checkers

  • 6+ years of experience in verifying complex designs both at the component and full-chip level

  • 4+ years of experience in SystemVerilog based OVM/UVM, VMM, or related object-oriented and coverage-driven ASIC verification methodology 

What is Being Offered:

  • Best-in-class compensation

  • Annual + Quarterly bonuses, stock programs

  • Cutting-edge health plan options

  • Generous time off

  • Life-long career growth opportunities

  • Education benefits: tuition assistance, classroom and online learning resources, career advisers

  • Relocation assistance

  • Flexible work options, job rotation programs

  • Wellness programs + Employee Assistance Plans/Programs